Marvell Technology is the latest chipmaker to join the emerging Universal Chiplet Interconnect Express (UCI-Express) consortium, which is working toward an open interconnect standard for chiplet architectures. The chipmaker joins several heavy hitters in the tech arena that have thrown their weight behind the project, including AMD, Arm, Qualcomm, and Intel to name just a few.
The UCI-Express 1.0 spec defines a standard means for heterogeneous die-to-die communication. It’s based on the Compute Express Link (CXL) protocol, which itself provides a common, cache-coherent interface for connecting CPUs, memory, accelerators, and other peripherals.
“This is an exciting opportunity to realize that vision someday of having multiple suppliers having dies in the same package and, for the customer, offering a much more robust solution than any one supplier can offer,” Hugh Durdan, vice president of Marvell’s ASIC business unit, tells The Next Platform.
UCI-Express effectively extends datacenter modularity down to the chip’s internals. Instead of baking all of the functionality you need into a single die, chipmakers can mix and match functionality using chiplets from multiple vendors. You can think of it like Legos for chip packaging.
For example, if you’re building a chip for an industrial environment that needs to process large quantities of visual data and then send it over the network, a chip could conceivably be assembled using a CPU from Intel, a GPU from AMD, and a switch ASIC from Marvell.
“That’s the vision. When or if it will be achieved is a little unclear,” Durdan says. “The vision is someday there could be a market for chiplets and multiple vendor’s silicon all in one package, but I think that’s going to take a little bit of time to develop.”
To be clear, chiplet architectures are by no means new. AMD has been gluing together chiplets to achieve higher core counts and better yields for years now. The problem is existing chiplet architectures rely on proprietary interconnect fabrics to glue the chips together.
It’s a similar story with Marvell’s own multi-chip platforms.
“The thing, quite honestly, is that most of the designs that we’ve done that have multiple chips [were] a closed system. It was our chips talking to our chips,” Durdan says. “The benefit we see to UCI-Express is just standardization. It’s great that we have our own proprietary interface, but getting that other party to adopt our proprietary interface is a lot harder than getting that other party to adopt an industry-standard interface.”
With that said, Intel once Frankensteined an AMD GPU into a mobile processor using its embedded multi-die interconnect bridge (EMIB) technology and PCIe 3.0 for communication with the CPU die.
In truth, the challenge isn’t whether you can make chiplets work, that’s already been solved for. Instead, the hard part is getting multiple vendors to agree on a standard way for how chiplets should talk to each other. And even this is addressed in part by CXL’s broad support.
Marvell’s decision to join the consortium isn’t surprising by any means. The company is no stranger to interconnects. In fact, they’ve acquired quite a bit of talent in this department over the past few years, most recently with its $10 billion acquisition of Inphi.
Marvell is also actively working with the Open Compute Project and Optical Internetworking Forum on a similar standard for connecting single or multi-node 5 nanometer and 3 nanometer chiplets. The company says it will continue contributing to the OCP and OIF projects even after joining the UCI-Express consortium.
“We see the great value in aligning interconnect standards across the industry and look forward to contributing towards that goal as a member of the UCI-Express consortium,” Marvell CTO Noam Mizrahi, said in a statement.
Marvell’s investments in CXL may also come into play here. The company has years of experience working on the emerging CXL standard underpinning the UCI-Express spec. The company recently detailed its CXL product portfolio, following the acquisition of Tanzanite last month.
It’s not hard to imagine Marvell offering a variety of CXL controllers as a chiplet. However, the company hasn’t said which IP it plans to offer as chiplets.
“The challenge, quite frankly, is we’ve had a hard time narrowing in on a spec that’s going to meet everyone’s needs,” Durdan says.
In many ways, Marvell’s decision to join the UCI-Express consortium feels like a natural extension of its existing efforts under its Custom ASICs division. That offering enables customers to develop chips that fuse custom or proprietary architectures with elements picked from Marvell’s own IP portfolio.
With that said, it remains to be seen how chipmakers will implement this technology, let alone who decides which chips can and can’t be packaged together.
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