• Hadoop Platform Raised to Knights Landing Height

    August 15, 2017

    It would be surprising to find a Hadoop shop that builds a cluster based on the high-end 68+ core Intel Knights Landing processors—not just because of the sheer horsepower (read as “expense”) for workloads that are more data-intensive versus compute-heavy, but also because of a mismatch between software and file system elements.

    Despite these roadblocks, work has been underway at Intel’s behest to prime Knights Landing clusters for beefier Hadoop/MapReduce and machine learning jobs at one of its parallel computing centers at Indiana University.

    According to Judy Qiu, associate professor of intelligent systems engineering in IU’s computing division, it is …

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  • Performance Portability on the Road to Exascale

    August 14, 2017

    The software ecosystem in high performance computing is set to be more complex with the leaps in capability coming with next generation exascale systems. Among several challenges is making sure that applications retain their performance as they scale to higher core counts and accelerator-rich systems.

    Software development and performance profiling company, Allinea, which has been around for almost two decades in HPC, was recently acquired by ARM to add to the company’s software ecosystem story. We talked with one of the early employees of Allinea, VP of Product Development, Mark O’Connor about what has come before—and what the software performance …

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  • An OS for Neuromorphic Computing on Von Neumann Devices

    August 2, 2017

    Ziyang Xu from Peking University in Beijing sees several similarities between the human brain and Von Neumann computing devices.

    While he believes there is value in neuromorphic, or brain-inspired, chips, with the right operating system, standard processors can mimic some of the efficiencies of the brain and achieve similar performance for certain tasks.

    In short, even though our brains do not have the same high-speed, high-frequency capacity of modern chips, the way information is routed and addressed is the key. At the core of this efficiency is a concept similar to a policy engine governing information compression, storage, and retrieval. …

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  • Engineering Code Scales Across 200,000 Cores on Cray Super

    July 19, 2017

    Teams at Saudi Aramco using the Shaheen II supercomputer at King Abdullah University of Science and Technology (KAUST) have managed to scale ANSYS Fluent across 200,000 cores, marking top-end scaling for the commercial engineering code.

    The news last year of a code scalability effort that topped out at 36,000 cores on the Blue Waters machine at the National Center for Supercomputing Applications (NCSA) was impressive. That was big news for ANSYS and NCSA, but also a major milestone for Cray. Just as Blue Waters is a Cray system, albeit one at the outer reaches of its lifespan (it was installed …

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  • The Biggest Shift in Supercomputing Since GPU Acceleration

    June 22, 2017

    For years, the pace of change in large-scale supercomputing neatly tracked with the curve of Moore’s Law. As that swell flattens, and as the competitive pressure ticks up to build productive exascale supercomputers in the next few years, HPC has been scrambling to find the silver bullet architecture to reach sustained exascale performance. And as it turns out, there isn’t one.

    But there is something else—something few saw coming three years ago, has less to do with hardware than it does a shift in how we approach massive-scale simulations, and is happening so fast that too-far-ahead-of-time procurements are …

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  • Python Coils Around FPGAs for Broader Accelerator Reach

    June 5, 2017

    Over the last couple of years, much work has been shifted into making FPGAs more usable and accessible. From building around OpenCL for a higher-level interface to having reconfigurable devices available on AWS, there is momentum—but FPGAs are still far from the grip of everyday scientific and technical application developers.

    In an effort to bridge the gap between FPGA acceleration and everyday domain scientists who are well-versed in using the common scripting language, a team from the University of Southern California has created a new platform for Python-based development that abstracts the complexity of using low-level approaches (HDL, Verilog). “Rather …

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  • HPC Center NERSC Eases Path to Optimization at Scale

    May 25, 2017 Rob Farber

    The National Energy Research Scientific Computing Center (NERSC) application performance team knows that for many users, “optimization is hard.” They’ve thought a lot about how to distill the application optimization process for users in a way that would resonate with them.

    One of the analogies they use is the “Ant Farm.” Optimizing code is like continually “running a lawnmower over a lawn to find and cut-down the next tallest blade of grass,” where the blade of grass is analogous to a code bottleneck that consumes the greatest amount of runtime. One of the challenges is that each bottleneck …

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  • A Health Check For Code And Infrastructure In The Cloud

    May 24, 2017

    As businesses continue their migration to the cloud, the issue of monitoring the performance and health of their applications gets more challenging as they try to track them across both on-premises environments and in both private and public clouds. At the same time, as they become more cloud-based, they have to keep an eye on the entire stack, from the customer-facing applications to the underlying infrastructure they run on.

    Since its founding eight years ago, New Relic has steadily built upon its first product, a cloud-based application performance management (APM) tool that is designed to assess how well the …

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  • One Programming Model To Support Them All

    May 24, 2017 Danny Bradbury

    Many hands make light work, or so they say. So do many cores, many threads and many data points when addressed by a single computing instruction. Parallel programming – writing code that breaks down computing problems into small parts that run in unison – has always been a challenge. Since 2011, OpenACC has been gradually making it easier.  OpenACC is a de facto standard set of parallel extensions to Fortran, C and C++ designed to enable portable parallel programming across a variety of computing platforms.

    Compilers, which are used to translate higher-level programming languages into binary executables, first appeared in …

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  • OpenMP: From Parallel Loops To Exaflops

    May 3, 2017 Rob Farber

    This fall will mark twenty years since the publication of the v1.0 specification of OpenMP Fortran. From early loop parallelism to a heterogeneous, exascale future, OpenMP has apparently weathered well the vicissitudes and tumultuous changes of the computer industry over that past two decades and appears to be positioned to address the needs of our exascale future.

    In the 1990s when the OpenMP specification was first created, memory was faster than the processors that performed the computation. This is the exact opposite of today’s systems where memory is the key bottleneck and the HPC community is rapidly adopting faster memory …

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