The Barcelona Supercomputing Center has launched the European Laboratory for Open Computer Architecture (LOCA), a five-year effort aimed at developing energy efficient, high performance computing chips based on open architectures. Although the resulting intellectual property is intended be available to anyone, the initial target audience is European users looking to build HPC systems powered by open source hardware.
The chips that LOCA will be exploring will be based on the three most popular open architectures of the day, namely RISC-V, OpenPower, and MIPS. According to LOCA director John Davis, Arm was excluded from consideration because it doesn’t fit this criterion. “Arm is not an open ISA, enabling hardware changes, and does not support the same open source development model at this time,” Davis told us. “If that changes, we would be more than happy to include Arm.”
The big potential winners here are OpenPower and MIPS, which are struggling to remain relevant in a world dominated by X86 and Arm. Despite high-profile supercomputers like “Summit” at Oak Ridge National Laboratory and “Sierra” at Lawrence Livermore National Laboratory, which uses IBM Power9 CPUs, overall market share for Power-based HPC systems is in the single digits. Its inclusion here in the LOCA work could help boost its prospects in this sector, not just against X86 and Arm, but also against the two other open architectures vying for attention. IBM open sourced the Power instruction set back in August.
MIPS is probably a longer shot here, in that, unlike OpenPower, its track record in high performance computing is limited (Silicon Graphics workstations and servers in the 1990s and early 2000s and SiCortex clusters in the late 2000s). Wave Computing, which now controls the MIPS technology, appears to be positioning the open architecture mainly for edge computing environments.
Davis noted that LOCA is only loosely aligned with the European Processor Initiative (EPI), an EU program whose goal is to develop domestic processor designs for HPC and other application areas deemed critical to European industry and research. The EPI HPC design will use Arm and RISC-V as the basis for its general-purpose CPU and accelerator, respectively, while also including a number of more specialized processing elements. The HPC processor is being groomed for eventual use in the first European exascale systems that are expected to start showing up in 2023.
The most obvious overlap between LOCA and EPI is the RISC-V accelerator, since both will support ecosystem development around this open ISA. Davis said the LOCA work could also line up with the MareNostrum Experiment Exascale Platform (MEEP), yet another EU project, this one aimed at developing emulation and software development infrastructure for future exascale systems.
One of the big drivers behind the LOCA work is the slowdown of Moore’s Law, which is encouraging the development of customized processors both across computing segments and across geographies. The rationale is that increased specialization can deliver the performance and energy-efficiency boosts that would have traditionally been supplied by smaller transistors on standard architectures. This trend is being accelerated by AI and machine learning applications, which, like traditional HPC, have computational demands that are advancing far faster than what can be delivered by commodity silicon.
The rationale for using open architectures is that they are more suitable for these more customized designs, inasmuch as they are easier to extend and thus specialize. This is particularly valuable when a codesign approach is used, as is the case here with the LOCA effort.
The five-year timeline on the project suggests that any resulting processors could end up in the second batch of European exascale systems that will come online around the middle of the next decade. Of course, as we already mentioned, since all this IP is destined to be open, any country or company could pick up these same designs and use them for their own purposes, HPC or otherwise.
Davis said the technology could eventually be extended to IoT, mobile, and edge platforms, since there are common IP elements across these applications that apply to all of them. But the initial thrust of this work is aimed at scientific and industrial workloads that typically run on HPC machinery.
“We will leverage the hardware to codesign solutions for bioinformatics, personalize medicine, real-time systems, self-driving cars, climate modeling, material science, AI and many other applications that reside within the research walls of the BSC,” explained Davis. “By using these applications to drive development, we hope this makes technology transfer to industry much easier and faster, with higher quality proven IP.”