Big Blue Open Sources Power Chip Instruction Set

It has been a long time coming, and it might have been better if this had been done a decade ago. But with a big injection of open source spirit from its acquisition of Red Hat, IBM is finally taking the next step and open sourcing the instruction set architecture of its Power family of processors.

Big Blue is also moving the OpenPower Foundation, which it formed with Google, Mellanox Technologies, Nvidia, and Tyan to help create an ecosystem around the Power architecture six years ago this month, under the administrative control of the Linux Foundation. (Considering how many open source projects are under the control of the Linux Foundation, perhaps it is time for that organization to consider a name change. The Open Foundation is probably appropriate, and probably already owned by someone else.)

In any event, if you have ever wanted to create your own Power processor and was lamenting how expensive it might be to license the technology from IBM, now is your chance.

IBM’s long journey to opening up the Power architecture began a long time ago, starting with the creation of the PowerPC Alliance between Apple, IBM, and Motorola back in 1991, just as Big Blue was starting to get serious about the Power architecture for RS/6000 Unix systems – Unix was all the rage then, and Sun Microsystems and Hewlett Packard were circling IBM’s proprietary mainframes and minicomputers like starving wolves, with a very lean and hungry Oracle snarling nearby. Behind the scenes, IBM was preparing to move its proprietary AS/400 enterprise systems to a common hardware platform with the RS/6000, a credible Windows Servers was years away (and would very briefly run on Power iron), and a young Linus Torvalds had just created the first Linux kernel (which would eventually be the key to keeping Power iron alive in HPC centers in particular and in some enterprise datacenters).

The history is long and complex, but suffice it to say that Motorola and IBM both had their challenges bringing server-class processors to market and the move to 64-bits was particularly difficult. Interestingly, it was IBM’s AS/400 processor team in Rochester, Minnesota which saved the day by creating a very good 64-bit PowerPC chip that also had a double-pumped vector processor embedded in it, and it is this processor, not the ones designed by the AIX people down in Austin, that is the very kernel of all Power chips and systems that have followed since. Eventually Sun Microsystems went up on the rocks with its UltraSparc-III systems, and Hewlett Packard and Intel created Itanium, which had its own litany of woes, and this left the door wide open for IBM to be a spoiler in the early 2000s. And it was just then, back in 2001, when IBM got its first dual-core chip and its first processor to clock above 1 GHz out the door – that would be the Power4 “GigaProcessor” – and IBM brought the hammer down in Unix, delivering twice the bang for the buck as Sun and HP did in Unix, eating market share like crazy.

At the same time all of this was going on, the Motorola 68000 series of chips, which were at the heart of Apple PCs as well as myriad kinds and untold millions of embedded controllers. Arm may rule in controllers today, but back then its was Motorola 68Ks, and the kind of unified processor architecture spanning from embedded devices to datacenter gear was first done – and actually realized – with the PowerPC architecture.

Of course, since then, the Unix market has been largely replaced by X86 systems running Linux and Windows Server, and Sparc from Sun and PA-RISC from HP, and Itanium from Intel are all dead. Motorola has ceded the embedded controller market to Arm, and IBM has been trying to breathe some life into Power, first through the in 2004 and the OpenPower Foundation in 2013. With each move, IBM has opened up its technology a little more and broadened its appeal. It is a question as to whether this will be enough, with an ascending AMD providing an alternative to Intel processors and the Arm collective fielding many good processors, all using Arm licenses and many adding their own special tweaks to the Arm designs while not violating the Arm architecture.

No one is saying that the OpenPower Foundation will have an easy time growing its ecosystem, despite the many architectural advantages that Power holds over other ISAs, but it now has an easier time than a more closed architecture has. It doesn’t hurt that the Power ISA is being given away royalty free, either.

“We started OpenPower six years ago because the industry was seeing the decline of Moore’s Law, and we were seeing the need for more powerful systems to support HPC, artificial intelligence, and data analytics,” Ken King, general manager of OpenPower at IBM, tells The Next Platform. “We needed to find other ways to drive system performance, and with limitations on the processor, the ability to integrate and innovate up and down the stack was becoming more critical. This led to things like NVLink with Nvidia, a close relationship with Mellanox on interconnects, and OpenCAPI for other devices, and we have seen some progress here. But we are also seeing a shift in the industry, with companies moving to more open hardware. IBM opening up Power to the point where we would license the CPU RTL to others so they could design their own processors was limited in its effect because there were not that many people who wanted to spend many hundreds of millions of dollars – not for license fees, but for full development – to create their own high-end CPU. We did make some progress in opening up our reference designs, and there are over 20 vendors who are now making Power-based systems. We are seeing interesting developments with the nascent RISC-V architecture, and hyperscalers are hiring their own chip designers and building their own CPUs and interconnects. They are getting into the hardware space, even if they are not going to be hardware vendors, to drive that performance.”

In that environment, now is as good time as any to get the Power ISA opened up and see what kind of uptake it might have against RISC-V and Arm and a closed X86 architecture from AMD and Intel.

To be precise about what IBM is doing, it is opening up the Power ISA and giving it to the OpenPower Foundation royalty free with patent rights, and that means companies can implement a chip using the Power ISA without having to pay IBM or OpenPower a dime, and they have patent rights to what they develop. Companies have to maintain compatibility with the instruction set, King explains, and there are a whole set of compatibility requirements, which we presume are precisely as stringent as Arm and are needed to maintain runtime compatibility should many Power chips be developed, as IBM hopes will happen.

The OpenPower Foundation, working under the Linux Foundation umbrella, will have an open governance model, with IBM having precisely the same one vote as other OpenPower Foundation members as to what changes can be made to the Power ISA in the future. IBM will have retain the right to make whatever changes that it wants to the architecture to suit its own needs, but all other changes will require a majority vote of the members to ensure compatibility. “Everything has to stay in the compliance guidelines because we do not want a bunch of fragmentation,” says King. This presumably also applies to Big Blue. If companies want to make a non-compliant change, it takes a unanimous vote of the members to do so. For instance, this may be for some specific set of instructions for a very precise workload set. Anyone can do a custom chip, too, but they will fall out of compliance with the ecosystem.

In addition to all of this, IBM is providing a softcore model of the Power ISA that has been implemented on FPGAs – presumably from Xilinx, not Intel’s Altera devices – that people can play around with.

In addition to this, IBM is also taking its OpenCAPI accelerator interface and its OpenCAPI Memory Interface variant, which is a key feature of the Power9’ (that’s a prime symbol, not a typo) processor that is coming out sometime this year, and it is actually contributing the RTL for these reference designs to the OpenCAPI Consortium, which is independent from OpenPower.

Some work needs to be done to reduce the number of communication methods and protocols that are being employed to link CPUs to each other, to accelerators, and to storage. Gen-Z, CCIX, CXL, OpenCAPI, NVLink, Infinity Fabric – the list keeps getting longer and the differences between them all are disruptive in a bad way. We need one or two standards, maybe. Perhaps this last bit is a step in getting us there. IBM just wants for companies to make OMI memory, which we have talked about before and which we will be detailing shortly based on a presentation that IBM made this week at Hot Chips. OpenCAPI memory may be the best way to get most of the bandwidth benefits of HBM memory without having to resort to stacking up and packing it up, but keeping it in DIMM form factors.

And so, right here right now, King is extending the olive branch out to Intel, much as it did back in the late 1990s when InfiniBand was created largely by Intel and IBM as a replacement for the PCI-Express bus.

“OpenCAPI and OMI are architecture agnostic, and the goal is to enable others to create their own coherent accelerator and memory interfaces in an open standards environment,” says King. “We are hoping over time – and we have been having these discussions – that with OpenCAPI we are able to work with Intel and converge OpenCAPI and CXL to converge them into one, common standard. And there is a lot of interest in that, without getting into the specifics.”

We suspect that Google, Facebook, and maybe a few others have some good ideas about how this might get done, and that this time around, they will have a big say on how these standards will converge. One thing is for sure: They won’t tolerate six standards when one or two will do.

Sign up to our Newsletter

Featuring highlights, analysis, and stories from the week directly from us to your inbox with nothing in between.
Subscribe now


  1. The biggest winner from this would be Microsoft. Within a year or two you will see Windows Server, MS SQL, C#, Office 365 and Microsoft cloud services powered by Power Chips. Microsoft will be a 2 trillion dollar company in 10 years.

    • Windows Server has to become a viable alternative to RHEL, CentOS, and other far more secure platforms, before it has even a remote possibility of seeing high adoption rates in Enterprise solutions. Not to mention that the closed Microsoft ecosystem is not at all conducive to enterprise level systems or markets.

      No, Microsoft likely stands to gain nothing from this at all. They will make products for POWER, sure…however…I doubt they see much in the way of adoption. Windows has less than 2% of server OS penetration now, and that number has not moved much in the past 20 years, and it will continue to be stable around that point for another 100 years unless they do something completely different than their current push to align OS across all platforms. The more their server OS continues to try to look like a mobile OS, the less appealing and more problematic it becomes.

  2. IBM did a lot to hurt the use of PPC (Power) chips in embedded products when it killed off it’s 15W PPC G5 chip around 2004, and ceased development of low power PPC chips ( 15 watt chips) that found use in the embedded processor market. IBM did that when Apple stopped using
    PPC / Power processors in it’s MAC PC’s and moved to using x86 chips
    in MAC PC’s. IBM should have at least found another company to keep making the 15 Watt G5. Killing off that chip hurt the embedded market greatly – a great chip was killed off, and development of more low power Power chips for the embedded market by IBM was ended also. Power chips used in IBM servers were then over 100 watts – a lot of power consumption for most embedded products.

    At the same time, Motorola Semiconductor (Later it became Freescale ) ceased development of new, much more powerful PPC cores for the embedded chip market in the early 2000’s. When Freescale went multicore, it used the older, slower G3, instead of the much faster G4 chip. Even when it brought out a PPC chip with 64 bit addressing, the 64 bit addressing core was not that much more powerful than the 32 bit G3 cores. So Freescale PPC chip cores were not getting much more powerful. And companies needing much more horsepower in processor chips used for embedded purposes moved to processors in other processor families.

    • Things is people got tired of waiting for IBM to came trough and open, now days even if they go open sourcing ISA including some designs it won’t help them much. Today only announced Power 9 has only one advantage over competition and that’s VFP processing unit design, when you add SIMD’s they don’t lead even there. But that is irrelevant as there are much better/faster DSP’s for the job. When it comes to basics that do mean a lot like simplicity and ISA layed ground for scalability the RISC V is a clear winer. Let’s call it’s simplicity as more than spiritual successor of M68000. By scalability I don’t mean on interconnects or clusters but a processing word width. The RISC V simplicity is a large advantage for wider scaling hire and ISA already has a finished 128 bit specification and 256 bit one is in the work. I don’t mean we will need a more than 64 bit address length anytime soon but a wider front end tied with multiple INT and VFP units will simply scale IPC on much higher lv than let’s say complicated OoO designs employed today while simple OoO will be easy to employ with the new RISC V. The result is 1.7x (when compared to the best to date OoO core’s like A73) to over 5x (when comparing to wide instructions per clock OoO core’s) area/power efficiency per same lv of performance. The IBM could significantly contribute to the RISC V architecture by opening & merging parts of it’s work including; additional instructions (part of it at least), VFP design, interconnects, power rails design which are all open book (not final) in RISC V world. There’s no need nor space to legacy architectural heritage to tie us down even if it becomes open source. Instead we need to learn from it and shape new & clean more then emerging but not yet established one. The future indubitably belongs to the multi & special purpose accelerators but we will always need general purpose CPU cores as they front end (& possibly this way as in generally a front end to all high parallel processing blocks with just one ISA [symmetric parallel built systems]).

      Best regards.

  3. Is that the full current full Power ISA, power9/10 included, and the MIPS ISA has been Open Sourced as well. So it’s not only the Power ISA that has a large and lengthy software ecosystem built up over the years as MIPS has been around as long as ARM with the MIPS software ecosystem being just as mature.

    RISC-V has some nice work and support but that software/firmware/optimized OS ecosystem does not develop itself overnight. And x86 and ARM are still propitiatory ISAs but also have mature software/firmware/OS(Optimized) ecosystems.

    Now just because the Power9/Power ISA is opened up does not mean that IBM’s specific hardware implementation that executes that now Open ISA is open, and ditto for any other MIPS ISA or RISC-V ISA running on others’ custom hardware implementations. Folks it’s the underlying hardware implementation that gets the real work done and an ISA is nothing more than a execution template that can have any specific custom hardware implementation being more efficient or less efficient depending on that in-hardware implementation that’s engineered to execute the ISA.

    RCA Spectra 70 is some interesting history(1) in relation to IBM’s 370 ISA, and that was not fully comparable because of the privileged 360 ISA instructions and the needed fixes required at the software/OS ecosystem level. And the OS/software ecosystem is needed for the application software ecosystem to ever have the ability to do its job without having to reinvent the wheels that make it all go round and round.

    From Wikipedia:

    “The RCA Spectra 70 was a line of electronic data processing (EDP) equipment manufactured by the Radio Corporation of America’s computer division beginning in April 1965. The Spectra 70 line included several CPU models, various configurations of core memory, mass-storage devices, terminal equipment, and a variety of specialized interface equipment.[1]

    The system architecture and instruction-set were largely compatible with the non-privileged instruction-set of the IBM System/360. While this degree of compatibility made some interchange of programs and data possible, differences in the operating system software precluded transparent movement of programs between the two systems. ”


    “RCA Spectra 70”

    • Yup. As the story pointed out, IBM has most definitely not opened up the RTL for the Power8 or Power9 chips and has no intention to. But these are, as they have been in the past, available for license. IBM knows it cannot charge a huge amount of money, and I would guess it has to be smaller than an ARM license if it wants to have any uptake.

      • Yes ARM have their reference design cores for those that do not have their on in-house chip design engineers. And Apple, Samsung, Qualcomm, Marvell(Cavium) have their in-house engineers that are very capable. And Arm Holdings has that ISA only “Architectural” license for the big boys to implement in any fashion that they can manage in custom hardware implementations along with some ready made core designs for the smaller less capable customers.

        So maybe IBM/OpenPower need to work up some Power9 Light core designs where they can license that RTL out to others with some actual blueprints for other less capable entities to license. ARM Holdings’ reference CPU core designs for license is actually what got the ARM ISA and its software ecosystem spread far and wide over the decades, that and Apple’s early involvement with Acorn RISC Machines(The Germ Of Arm Holdings).

        So Big Blue maybe needs to Tape Out some lesser Reference Design Power core for license and that Power-Lite core that can be licensed out at low cost as a starting point as well in addition to opening up the ISA ONLY for usage by other more capable design houses’ custom core designs that can now also legally be reverse engineered cores designed to execute that Power ISA.

        MIPS is also a player with a mature Software/OS/Firmware ecosystem something that the RISC-V folks and their membership will have to develop out in order for that RISC-V to have a Competitive chance. IBM’s Linux based software/firmware ecosystem can be it’s biggest selling point and there are currently from Raptor Computing Systems some Power9 based PC and Server systems that ship with Open Source Firmware(OpenBMC Project based) and some 4 and 8 core Power9 variants, larger core counts as well. Raptor Computing Systems will sell any Home Builder the MBs the CPUs and other components as well so maybe that’s how some folks can get their hands on experience with Power9.

        The really good news that extends from IBM/OpenPower Opening up that Power ISA is that that ISA will live on, regardless of IBM’s needs or desires, in the hands of others and that can not be undone. But there will need to be come other Power ISA only licensee that can engineer their own custom hardware IP to execute that ISA. Even ARM Holdings, Apple and the others can create that as well and use or license out core designs that execute the Power ISA.

        Why even Intel or AMD could as well but Nvidia really needs to look at that or RISC-V so Nvidia could maybe be a dual CPU and GPU dual sword wielder like the other main competition, Intel is planning on reentering the Discrete GPU market once again starting some time in 2020. I’d love to see some Nvidia based Power9’s and Nvidia already makes use of RISC-V with their Falcon line of controllers that Nvidia makes use of on GPUs for various secondary encoding/decoding and other management tasks.

        The lack of a Mature Software/Firmware/OS ecosystem is the main limiter to any Open ISA seeing wider use in the market and software/OS/Development development costs are what limited RCA at that time, and that still holds true to this very day.

        Perhaps RTL(Resistor–transistor logic) is easily looked over if it has not been parenthetically defined at least once and acronyms are easily overlooked often. Blueprints maybe or even Verilog the digital equivalent of blueprints.

          • There is a whole Wikipedia disambiguation entry for the acronym RTL and that’s the very reason that in academic papers/articles all acronyms should be defined at first use, either by reference or by parenthetical entry.

            So there are 5 definitions under the Electronic subheading alone for RTL:

            Prefix for some Realtek integrated circuits
            Register-transfer level or register-transfer logic, of a digital logic circuit
            Register transfer language, a type of computer language
            Resistor–transistor logic, a class of digital circuits
            Rudder travel limiter, an aircraft control device ” (1)

            And that’s why Acronyms need to be defined at least once so folks are not having to look things up and run into Acronym Overloading.




Leave a Reply

Your email address will not be published.


This site uses Akismet to reduce spam. Learn how your comment data is processed.