At the recent EuroHPC Summit in Poland, the nature of Europe’s first homegrown HPC processor was described in some detail. The design incorporates Arm, RISC-V, high bandwidth memory, and other technologies in a multi-tile package that will be used to power Europe’s first exascale supercomputers. The work is being performed under the European Processor Initiative (EPI), an EC-funded project whose aim is to develop indigenous chip technology for HPC, AI, and other application areas.
During the EuroHPC event, EPI general manager Philippe Notton outlined the architecture of the HPC package in broad strokes and revealed the existence of SiPearl, a fabless chip company that will license the EPI intellectual property and bring the exascale processor to market. Notton, who founded the company, also provided a roadmap for its products.
The timeline shows the first-generation SiPearl chip, codenamed “Rhea,” is scheduled for a 2021 release. The Rhea chip will go into exascale prototype machines, and will be used to help test the EPI technology for the first European exascale supercomputers coming in 2023. The production exascale systems will presumably be powered by SiPearl’s second-generation HPC chip, known as “Cronos,” which is expected to be ready as early as 2022. An unnamed third-generation SiPearl chip is also on the roadmap, presumably for the second wave of exascale systems in Europe. SiPearl also intends to build chips for AI, big data, and automotive markets, and if all goes according to plan, will eventually develop silicon for the enterprise server market as well.
The Next Platform spoke with Notton, along with EPI chair Jean-Marc Denis, about where the research and development effort currently stands and the various chip technologies under development. This is Europe’s first real foray into high-end processor design, and as both Notton and Denis admitted, requires a certain pragmatism in order to move the work forward. Even the original aspiration to deliver an all-European processor to the EU has had to adapt to certain events on the ground, as well as the realities of the global semiconductor supply chain.
In particular, when Arm Holdings was acquired by Japanese-based SoftBank, that basically killed the notion that this would be a purely indigenous platform. Of course, even if Arm had maintained its independence as a business based in the United Kingdom, Brexit would have rendered its European credentials somewhat suspect. All that aside, the inclusion of other technologies like PCI-Express and high bandwidth memory would have made the platform something less than perfectly European.
The package infrastructure, which will be based on 2.5D interposer technology, will also be imported from overseas. Today, there are only two established implementations of 2.5D packaging for high-end processors: Intel’s Embedded Multi-die Interconnect Bridge (EMIB) and Taiwan Semiconductor Manufacturing Corp’s Chip-on-Wafer-on-Substrate (CoWoS). Notton and Denis would only confirm they are definitely not using Intel’s technology. So there’s that.
The most critical designs for the SiPearl chips will indeed be developed within the European Union. That includes the Arm design itself. Although the architectural IP is licensed from Arm Holdings, the EPI implementation will be designed specifically for supercomputing. The Arm tiles will act as the host processor for the other auxiliary processors on the device. Other European components include a RISC-V-based HPC accelerator, a multi-purpose processing array (MPPA), which will be suppled by French chipmaker Kalray, and FGPA functionality, which comes from French-based Menta.
“The HPC platform integrates all these elements,” Notton told us.
The MPPA technology is designed for high-performance embedded computing, datacenter networking, and storage function acceleration. In the EPI/SiPearl context, its most obvious target is for autonomous vehicles, but its presence on the HPC platform provides the opportunity to do things like data reduction and transformation on real-time datastreams.
The FPGA component offers the ability to fix platform bugs or to accommodate a changing standard on the fly, avoiding the need to replace the hardware. Of course, the FPGA piece can also be used as a reconfigurable accelerator on the platform for specialized HPC workloads.
For the Arm design, the EPI engineers will be incorporating the HPC-level vector processing capabilities using the Scalable Vector Extensions (SVE) created initially by Fujitsu and Arm for the “Post-K” ARM64FX processor used in the future Fugaku exascale system at RIKEN lab in Japan. Although Notton and Denis wouldn’t say, we think it’s possible and even likely that they will be using the newer SVE2 technology. That second-generation vector capability was announced by Arm in conjunction with a new Transactional Memory Extension (TME) capability, another HPC-oriented add-on that can be used to boost performance and scalability for parallel software. Our guess is the EPI team will glue both technologies into its exascale processor.
EPI is also developing a custom HPC accelerator based on the open source RISC-V architecture. The EPI accelerator, also known as EPAC, will be comprised of up to eight vector processors that share L2 cache via an on-chip network. A special-purpose unit to speed up stencil operations will also be included alongside the vector processors to further boost performance on computer simulations and other types of codes that rely on stencil structures. EPI will also be developing a RISC-V-based accelerator for AI that includes a specialized deep learning unit, but this EPAC won’t be part of the HPC processor platform.
The EPAC customized for HPC will show up as another tile alongside their Arm masters. Although the exact ratio between the Arm cores and the RISC-V-based accelerators is unknown at this point, Notton estimates about 80 percent of the tiles in the first-generation HPC processor built by SiPearl will be Arm-based.
Although it might seem redundant to include a separate HPC accelerator alongside an already vector-accelerated Arm host, Denis says the rationale to have both on the device is to provide developers with the flexibility to use either the general-purpose SVE capability for the sake of simplicity or employ the more customized HPC accelerator to optimize execution speed and performance per watt. We’ll see how that plays out in the real world once the initial exascale machines come online.
Here’s where it gets more interesting though. According to Notton and Denis, RISC-V would be the preferred architecture for both the accelerator and the host and in fact, it’s certainly possible to implement a standalone chip for both, in the manner of the “Knights Landing” Xeon Phi from Intel. At this point, Arm has taken the lead role because of the maturity of the hardware technology and the associated software ecosystem.
But, as mentioned previously, Arm is fundamentally a non-European architecture. Plus, it entails licensing fees, whereas RISC-V, as a free and open source architecture, does not. But the use of RISC-V is something of a risk, especially considering that existing implementations of the architecture are almost exclusively aimed at embedded computing, which generally has more modest demands than HPC.
Going forward, the balance of power between Arm and RISC-V on EPI platforms will be determined by a number of factors, including how well RISC-V is accepted by the marketplace, and thus how fast the ecosystem grows around it, but also how Arm responds to the threat of RISC-V as far as its licensing policies.
“The long-term ambition we have is use fully European IP,” says Denis.
The EU is playing the long game here. If the member countries had opted to use chips from Intel, AMD, Nvidia, or other US-based chipmakers, they almost certainly would have been able to field an exascale system a year or two earlier than 2023. But there is a growing desire on the continent to be independent of foreign-born IT technology, along with a newfound ambition to develop a domestic chip industry and supply chain.
To accomplish that, Europe has opted out of exascale race, which, truthfully, is a small price to pay if the effort results in a domestic processor industry. The hope is that this will help not only enable Europe to establish itself as a supercomputing power on par with that of the US, China, and Japan, but also determine its own digital destiny in the broader IT realm.