Drilling Down Into The SiPearl European Arm Server Chip

The European Union has made it clear that it wants to be able to stand on its own two feet in the design of server processors, for both general purpose uses and for exascale-class supercomputers. It is a difficult task, and one that Silicon Pearl, a French startup founded by Philippe Notton, is taking on.

It has not been surprising to us at all that the European Union is funding the creation of its own server processors with matrix math and FPGA accelerators also coming from European suppliers. What is funny to us is that no matter how hard Europe tries, there is still a strong connection to the United Kingdom, which ironically is in the middle of its Brexit process to untangle itself politically and economically with the European Union.

It was a forgone conclusion that unless the European Union wanted to fund its own instruction set, or a clone of the X86 instruction set controlled collectively by Intel and AMD, that it would use an Arm design of some sort. Of course, Arm Holdings, which licenses the Arm chip intellectual property used in some servers but in a lot of smartphones, tablets, and various kinds of controllers, embedded systems, and telecom gear, is a British company with a long history in computing that is owned by SoftBank, a Japanese conglomerate. It would not be surprising to us that machines based on an indigenous European processor would be encouraged to run the Ubuntu Server variant of Linux, which is controlled by Canonical, a company based in the United Kingdom (had Brexit not been happening, of course), or SUSE Linux (which was controlled by Micro Focus International, also a British company, but has deep roots in Nuremberg, Germany and has been recently spun back out to its freedom). This would all be a much simpler and cleaner European story if the United Kingdom would just give up on Brexit. That said, SUSE Linux is German once again so it can be the preferred Linux for Europe, and SiPearl, as Notton’s company is nicknamed, is based on the west side of Paris with a development lab on the French Rivera, and it is hard to get more European than that.

We covered SiPearl in passing as part of the European Processor Initiative back in June last year. And now that SiPearl has gotten its initial funding of €6.2 million (about $6.7 million) and hired its first ten employees and taken down a license for the “Zeus” Neoverse N2 cores and related technologies from Arm Holdings to begin the design of the first generation of “Rhea” Arm server processors, we thought it would be a good time to sit down with Notton and have a chat about what SiPearl is doing both in conjunction with the EPI effort and as a separate company with its own aspirations in the Arm server chip space alongside Ampere Computing, Marvell, and Fujitsu, who are the three main players here.

Notton is no stranger to semiconductors. He got his electrical engineering degree, with a specialty in signal processing, from CentraleSupelec in Paris back in 1993, and worked on processors for digital setup boxes at Thomson Broadcast and then Canal+ in Paris for six years before landing jobs as a field application engineer for LSI Logic and Microsemi. Notton then did a stint at as a vice president at Mstar Semiconductor, which makes ASICs for various consumer and image processing products, before moving to STMicroelectronics as a group vice president for its Mass Market Multimedia division, where he was in charge of over 2,400 engineers working on a number of products. In June 2017, Notton joined Atos, which owns server maker Bull, to head up its processor initiative and was named general manager of the European Processor Initiative. In June last year, Notton became chief executive officer of SiPearl, which is tasked with designing and delivering the Arm server processors envisioned by the EPI, which he will remain general manager of until the end of June 2020.

Notton tells The Next Platform, the number of engineers working on the SiPearl Arm server chips – Rhea is the first generation and Chronos is the second generation – will grow to around 200 over the next two years as Rhea is created, tested, and ramped. All of that is predicated, of course, on SiPearl raising more funding to support the effort, which Notton will start doing in earnest this year as the company is now launched and initially funded.

Roadmaps are always a tricky business in the chip industry, and the one shown above shows the cadence but the time is likely going to slip a bit. The first generation Rhea chip will be etched in the N6 processes from Taiwan Semiconductor Manufacturing Corp, which is what some would calla 7+ nanometer process as is shown on the Arm Neoverse server chip design roadmap. (N6 is an enhanced 7 nanometer process that shrinks down to 6 nanometers and employs extreme ultraviolet lithography to get there.)

The Rhea ramp was originally slated for sometime in 2021 to 2022, but Notton says that full production of Rhea is now expected at the end of 2022 and adds that Chronos is probably going to be in 2024, not in the range of 2022 to 2023 as the roadmap above suggests. The first bubble in shown in the roadmap above is for the design of the Rhea chip and the second bubble is the ramp towards production. The third bubble is for the Chronos chip, also based on the Zeus core and presumably using the shrink down to 5 nanometers that is consistent with the Arm Neoverse server chip design roadmap. The unnamed third generation SiPearl chip is probably aligned to the “Poseidon” core from Arm, which is using 5 nanometer processes at TSMC. But Notton did not confirm that, and we suspect that this chip might come out in late 2025 to earl 2026. It is so early in the game for SiPearl that is it not even fair to call this roadmap slippage. This is the nature of starting up with a new company and taking on a big task of laying out billions and billions of transistors for a complex processor.

The Zeus license was absolutely necessary for SiPearl to hit the ground running, and mirrors what Ampere Computing did more than two years ago when it bought the assets from Applied Micro and dumped the homegrown X-Gene cores Applied Micro had been using in favor of the “Ares” cores in Arm’s Neoverse N1 designs for it “Quicksilver” Alta Arm server chips, which were just unveiled in March.

“SiPearl is business oriented, and we have three years to make a chip,” explains Notton. “And when you have three years to make a chip, you cannot recreate everything from scratch. It is physically impossible. For some of the components, the decision is to make or to buy, and to make them, you need to have a team already in place. And for some components, especially for the core, it would be impossible to make. We don’t have time. Marvell has a strategy of making their own cores, and they have a team and they started a while ago. Ampere is using Arm cores for the same reason we are. And today, even if you gave me the budget to design my own core, I am not sure that this is the best strategy. Arm has cores and they are working, and as a first design from a new company, we have to limit the risk. As to why Arm and not another core? For RISC-V, it is too early, and definitely so for a general purpose processor. X86 is not officially licensable and it is a bit too US-centric for what we are doing. And for us, Arm is much more neutral and what they are doing for HPC makes a lot of sense.”

As for Rhea, Notton is keeping mum about how many cores it might have, but says that “the cores are quite large so you can’t just put 200 of them on a chip.” That is not a statement about relative core sizes so much a statement that all compute cores are pretty big. Our guess is the core count will be somewhere around 100, give or take, given the process and the fact that Arm itself says the design is optimized for between 64 cores to 128 cores in a socket. That can be done with chiplets or on a monolithic die, and while Notton won’t talk about chiplets, we suspect that like Ampere Computing, SiPearl will put off moving to chiplets until later in its roadmap. You don’t want to tackle 7+ nanometer, a new design, and chiplet packaging all at the same time. There is a good chance that the Chronos chips in 2024 will employ chiplets for cores with a central I/O and memory hub implemented separately, all in the same N6 process, and that the third generation SiPearl chip (as yet unnamed) will move the cores to 5 nanometers and keep the I/O hub at the same N6 process.

There are a lot of ways to play this, obviously.

The Rhea chip will support both DDR4 and DDR5 main memory as well as HBM main memory (we don’t know if it is HBM2 or HBM3 memory, but we will lay odds that it is the latter, more modern variant). Rhea will also sport PCI-Express 5.0 peripheral controllers and will support the CCIX protocol for hoking up accelerators over PCI-Express. When we asked if the CXL protocol from Intel, which also runs atop PCI-Express 5.0 transports, would be supported, Notton said no comment, and he similarly did not want to comment on whether CCIX ports would be used to create NUMA machines. Obviously, given the Neoverse adoption of CCIX as transport for NUMA shared memory clustering for processor sockets, this is not only possible, but sometimes desirable when customers need more I/O and memory bandwidth and capacity against a certain number of cores. We would not be surprised to see two-socket Rhea machines or even four-socket ones, but anything larger than that would be surprising in a NUMA context.

The SiPearl chips will have various kinds of accelerators bundled in the CPU package and also has the capability of bundling in other accelerators as well as HBM memory onto the package using TSMC’s CoWoS interposer technology – the same that is used by Nvidia and AMD for their respective Tesla and Radeon Instinct GPU accelerators.

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  1. I can’t see how this will work. Sipearl is talking about delivering a range of chips years after other suppliers have already released parts based on similar technology.

  2. It will be interested to see how it does, but given this and Zeus being a high-end core, it’s likely most of the achieved FLOPS are from Arm’s SVE. While the chip will have ARM tiles, that’s mostly for the mainstream code according to https://redbytesite.com/, data preparation, orchestration etc. where RISC-V isn’t competitive today.

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