Ventana Sees Window for Robust RISC-V Server Business

The field is littered with the remnants of Arm and RISC-V server startups. While the wounded have been taken in from the armies of large chipmakers, bandaged up, and sent home to find a new calling, some climb back into the fray — faithful as ever to the dream of a successful open-source hardware future.

The new battlefield is the largest, which might be why so many ex-Arm/RISC-V veterans are soldiering back.

Hyperscalers are all dead set on developing their own processors. But moving from concept to reality, even with their legions of hardware and software developers, is still a minimum two-year, $25+ million effort. Perhaps the weapon of choice is the mighty chiplet — one that is battle-tested, accelerator-ready, and can camouflage with the host CPU to make custom SoC development cheaper and quicker. But it has to be open and expandable — otherwise, why would it be worth fighting for?

Ventana Micro Systems thinks there is plenty of fight left in the open hardware market, even after a series of past losses on the Arm front from its founders. They are pulling together a cache of critical technologies in chiplets, packaging, interconnects, and software to up the ante, especially for coveted hyperscale and OEM businesses.

Armed with $53 million in capital — including quiet early investments from Cisco, which has been a partner since the beginning — Ventana marched out of stealth this week with recognizable veterans, including Greg Favor, who was one of the forces behind the AMD K6 architecture before moving through a few startups and landing at Applied Micro and then Ampere (which itself spun out of Applied).

Co-founder and CEO Balaji Baktha also has a long background in architecture, although most frequently and recently on the investment side. In 2010, he founded Veloce Technologies, which aimed to create the first 64-bit Arm processor. This company was acquired by Applied in 2017 and Baktha says much of this technology helped Applied Micro spin out its own Arm processor, which later translated into elements of Ampere’s technology.

It has been a tough slog for Arm server technologies to reach anything near mass market. So what changed or is shifting now to make this different?

The market wasn’t ready for the Veloce 64-bit Arm technology, and Baktha says this gave him insight on how to prepare for more fertile ground.

“When we started, TSMC was the only fab we could use and was two process nodes behind Intel. To try to compete at that disadvantage as a problem. Also, the software ecosystem investments from Arm were not adequate. They didn’t put a lot of money to work and couldn’t push the ecosystem forward. That work was left to the silicon folks at Applied and Qualcomm for example.”

Fab issues, a lack of software support, and commitment from a wider community kept his Arm ambitions at Bay and he turned his attention to work being done at Berkeley in 2017 on RISC-V. “We decided RISC-V was an architecture with legs that would let us finish the job we started at Veloce.”

Baktha says they had a more productizing focus with Ventana after watching Arm go through the paces. He says they’ve been in conversations with all the hyperscalers and OEMs along the way to ensure they’re building what the market needs. This work began with Cisco. “They proposed a Series A to work with us and make sure this was productized in the right way. They led our Series A with $15 million while we were still in stealth.”

The end result is a chiplet that he says can speed custom device creation by years and save $20 million or more. The time might be right given all the hyperscalers are in a rush to create their own domain-specific processors, but don’t want to have the long lead times and engineering challenges.

“If someone productized our IP, they can do so expediently. If you look at conventional methods, you get MIPS or Arm IP and have to get soft IP then harden it. That takes two years or more and over $20 million getting set with the core, the foundations and libraries, the interconnectivity piece, then testing and full SoC tapeout,” he explains.

Ventana delivers its IP in a 16-core CPU cluster in 5nm as a known good die in chiplet form à la AMD. “We prove everything in 5nm and give customers a fully functioning silicon device. They can glue that chiplet to their SoC using a standards-based parallel interface that can allow them to rapidly productize an SoC.”

For customers that want to follow the Amazon route (for instance, Graviton) to creating their own devices, it’s the SoC where the possibilities are. Users can decide what they want that chiplet to emphasize (different memory sizes, PCIe lanes, etc). The major feature is that the high-speed parallel interface (which they provided no details about) is that it appears native to the CPU core. That means architects can add accelerators that operate at silicon speed instead of working in a staged pipeline through PCIe.

“This is cache coherent. The data can remain in the host CPU and the accelerator can be called out as a function using a C/C++ type framework.” He adds that they will provide a reference platform to customize or Ventana can do the work. Ultimately, they can tape out in three quarters, Baktha says.

All of this comes at the right time. There has been a notable swing back to domain-specific processors, especially for the largest consumers of compute. But Arm is too caged to let the largest companies have true flexibility in the SoC and engineering teams are in for long delays, despite ample in-house resources. Cost too is quite a factor, but that is a complicated equation in 2021.

The possible appeal of these capabilities is clear, but to what degree openness is truly achieved is still a bit tricky to parse. That parallel framework they’ve developed to the host CPU is a standard — but not an open standard. And that reminds us of those battles waged for so many years on the open hardware front: it’s open as a concept, but in practice, all architectures are caged in one way or another. Ventana is tackling a lack of interoperability, something that has been especially painful for open-hardware startups, by using OCP’s Open Domain Specific Architecture (ODSA) standard for its parallel die to die communications.

“Nearly half of compute spend is moving away from general-purpose processors in favor of infrastructure compute and domain-specific accelerators,” said Baktha. “Ventana is perfectly positioned to capitalize on this trend with our high-performance cores built on the extensible RISC-V architecture, and our chiplet-based rapid productization approach.”

As of this week, the company raised yet more capital with $38 million in a Series B funding round. The round was led by Dr Sehat Sutardja and Weili Dai (founders of Marvell Technology Group) and other prominent semiconductor investors in partnership with Series A investors — which include that notable strategic partner, Cisco — bringing Ventana’s total funding to $53 million.

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