In the past five years or so, we have had a remarkably good – and predictable – run of increases in aggregate switching bandwidth out of the major ASIC suppliers, and it has been a boon that underpins the massive expansion in datacenters among the hyperscalers. Many things have come together to allow for this bandwidth boom, not the least of which being switch ASIC vendors moving to the most advanced manufacturing processes to get advantage over one another in terms of cost and power per port.
While there are still good times ahead, there will come a day in the not-too-distant future where things will get more difficult, and the inevitable Moore’s Law wall will slow down the pace of change as it has done in compute engines for the past several years.
This, contends Mike Zeile, vice president in Intel’s Data Center Group and the lead in the strategy office for the Connectivity Group at the chipmaker, is why we are going to need more than incremental innovation in datacenter switching in the coming years. Zeile gave the keynote for the networking portion of our recent The Next I/O Platform event in San Jose, and also sat down and talked to us about the challenges that the industry is facing and how Intel – particularly in the wake of its acquisition of Barefoot Networks – intends to face them down.
“We are keeping pace quite nicely, and there are not too many complaints,” Zeile explains. “But I do think as you look closely at the SerDes, it’s a really hard problem now. We are having to design specific SerDes for specific use cases – I can get across the chip, but not outside the chip, or I can get outside the chip and do a couple of inches, but the I have to have repeaters everywhere. Repeaters are going to just be a common part of the design. We are running into limitations that are consuming power and creating limitations. Our perspective, of course, is that we will see people turn the crank on SerDes technology, but it’s getting harder and harder and it is getting super costly.”
As for the Barefoot Networks acquisition, Zeile says that this is a demonstration that Intel is back in the Ethernet switching business. Intel, of course, acquired Fulcrum Microsystems, the upstart, low latency Ethernet switch maker that Zeile was president of back when the deal was done in July 2011, and we have been, like many observers of Intel, perplexed as to why the chip maker did not more aggressively move into merchant switching silicon. But with the Barefoot Networks deal and the moth-balling of the Omni-Path flavor of InfiniBand, Intel is demonstrating that it is serious about Ethernet. In addition to the “Tofino” family of programmable switch ASICs, Barefoot Networks gives Intel control of the P4 programming language and its compiler, which was created by Barefoot Networks and which can be extended to other devices on the network – notably the network interface cards on servers and storage. The switch chip startup had also created very sophisticated telemetry and monitoring tools that worked in conjunction with its ASICs, which gave a much broader and deeper insight into what is going on in the network.
In addition to the Barefoot Networks acquisition, during the interview at The Next I/O Platform event, we asked Zeile about what Intel’s plans were for the Compute Express Link system interconnect and the prospect of creating very intelligent SmartNICs that offload all of the networking and storage interfaces from the CPU compute complex – much as Amazon Web Services has done with its “Nitro” family of SmartNICs. If you want to hear about that, you need to watch the video above.
As for the long-term answer to the issues that will soon be affecting the networking industry as Moore’s Law runs out of gas and clever SerDes engineers run out of tricks, at least as far as Intel is concerned, the trick will be to embrace silicon photonics. And in Intel’s case, that means using the same manufacturing techniques for networking circuits as are used for etching CPUs to take a combined compute-networking package mainstream.
Zeile’s keynote talks about inflection points, and the first one being Fulcrum’s original plan to create low latency switches that would allow for datacenter networks to scale out further than they could a decade ago. Think for a second about the high mark that the Fulcrum switch, at 150 nanoseconds of latency, and the Fulcrum router, which could deliver 200 nanoseconds of latency, still sets for the Ethernet market – even today. Nothing comes even close to that. Barefoot Networks, with its programmable data plane and good thermals and performance compared to fixed function ASICs, is another inflection. But there is a third one that is coming, says Zeile, and that is integrated photonics or optical I/O, however you want to call it. There are a slew of innovations that will be necessary for silicon photonics to do as well as the track for SerDes technologies, and even if it does not look like they will converge any time soon, Zeile thinks that it could happen in around five years.
“We are making a lot of progress, and we are doing a lot of great work,” Zeile says not just of Intel, but the networking industry in general. “I think we are getting close to really delivering optical I/O and so for those of you in the room who happen to be working alongside Intel in this space, thank you for your support and I think we are going to be able to celebrate really soon. And for those of you who remain skeptical, I certainly hope that you can cheer us on from the sidelines.”
The Next Platform will certainly be doing that because it is hard to imagine SerDes running faster than 100 GHz on the few remaining process shrinks we have left in chip manufacturing.
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