Towards 50Gbps SerDes and beyond

The end of Dennard Scaling and slowdown of Moore’s Law couldn’t have arrived at a more inopportune time for the semiconductor industry. To be sure, the burgeoning Internet of Things (IoT) has ushered in a new era of pervasive connectivity and generated an almost exponential growth of data. In parallel, semiconductor design costs have increased significantly, with expensive masks, complex fab processes and little room for costly re-spins due to time-to-market (TTM) demands. Nevertheless, the industry continues to demand more bandwidth and faster speeds, particularly for high-speed serial links (SerDes).

“From the age of chips communicating at 1Gbps to 10Gbps to 40Gbps to 100Gbps and setting the stage for 400Gbps and 1Tbps in coming years, everyone wants to communicate faster and faster but at the same time by being more efficient (energy consumption) and smaller (silicon area),” Mohit Gupta, director of SerDes product marketing at Rambus, explained.

“With new technology nodes trending even faster than Moore’s Law, there are a variety of dimensions and tradeoffs which are required to define a viable, next-gen SerDes.

According to Gupta, there is a definite need – in the short-term – to move from a 10Gbps serial link data rate to 25Gbps(already being deployed) or 50Gbps and perhaps even higher at 100Gbps as bandwidth and capacity requirements continue to scale up. There is already interest in community to look at Silicon photonics based solutions for 100/112Gbps.

“Shifting to higher data rate links in data centers and servers improves overall efficiency. For example, a 100GbE implemented in 10x10Gbps configuration significantly bolsters overhead, especially in comparison to 4x25Gbps systems,” he explained. “Of course, higher data rate SerDes are more complex and challenging to design. For example, systems need to run higher speeds (2.5x) for the same cables, traces and backplanes – all while supporting backwards compatibility for legacy standards running at 1.25Gbps.”

Gupta also noted that the power-performance ratio is another important variable to keep in mind when it comes to increasing data rates.

“Perhaps the biggest cost involved in running a data center is electricity consumption,” he added.

Typical Data Center Operating Costs Breakdown

“As such, there is a considerable amount of emphasis on keeping the power low for such links – even though they are targeted for higher speeds. This poses additional challenges for both system and serial link designers.”

The ideal paradigm for a high-speed SerDes, says Gupta, is one that maximizes performance with the lowest power draw and smallest area. However, a more realistic scenario would see compromises on performance, power and area, with trade-offs based on specific product requirements.

“For example, say a system requires a 56G SerDes supporting 35dB+ channel loss performance. What are my options as an engineer? Well, I could consider a traditional analog solution, although this would make it somewhat difficult to achieve high performance. Yet, it is area and power efficient,” he continued. “But what if I went with an ADC+DSP solution? This would allow me to achieve higher performance at scale, although I would have to contend with an increase in power draw and silicon area.”

These considerations, says Gupta, often prompt more questions than answers, including the following:

– Can I use lower reach SerDes which is cheaper on power/area and use additional components on board like re-timers and still stay within the same budget?

– Can I use a different and expensive board material which still supports same reach but has lower loss and thereby save on ASIC cost to compensate?

– Do I really need to support 1.25Gbps operation on 56G SerDes, can I constrain the usage?

– Is the channel smooth enough to take off some SerDes Equalization to maximize power and area efficiency?

– Can I eliminate extra pll/vco’s?

Rambus SerDes Solutions

“Deciding on a particular set of tradeoffs for high-speed serial links may very well be one of the most stressful parts of the entire design process,” Gupta concluded. “Nevertheless, optimally maximizing performance with the lowest power draw and smallest area is key to differentiating your high-speed SerDes at 50Gbps and beyond.”

Interested in learning more about designing high-speed SerDes? You can check out our R+ SerDes PHY product page here.