• Stanford’s TETRIS Clears Blocks for 3D Memory Based Deep Learning

    March 7, 2017

    The need for speed to process neural networks is far less a matter of processor capabilities and much more a function of memory bandwidth. As the compute capability rises, so too does the need to keep the chips fed with data—something that often requires going off chip to memory. That not only comes with a performance penalty, but an efficiency hit as well, which explains why so many efforts are being made to either speed that connection to off-chip memory or, more efficiently, doing as much in memory as possible.

    The advent of 3D or stacked memory opens new doors, …

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  • 3D Memory Sparks New Thinking in HPC System Design

    February 21, 2017

    Whether being built for capacity or capability, the conventional wisdom about memory provisioning on the world’s fastest systems is changing quickly. The rise of 3D memory has thrown a curveball into the field as HPC centers consider the specific tradeoffs between traditional, stacked, and hybrid combinations of both on next-generation supercomputers. In short, allocating memory on these machines is always tricky—with a new entrant like stacked memory into the design process, it is useful to gauge where 3D devices might fit.

    While stacked memory is getting a great deal of airplay, for some HPC application areas, it might fall just …

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