• Squeezing The Joules Out Of DRAM, Possibly Without Stacking

    March 23, 2017

    Increasing parallelism is the only way to get more work out of a system. Architecting for that parallelism required requires a lot of rethinking of each and every component in a system to make everything hum along as efficiently as possible.

    There are lots of ways to skin the parallelism cats and squeeze more performance and less energy out of the system, and for DRAM memory, just stacking things up helps, but according to some research done at Stanford University, the University of Texas, and GPU maker Nvidia, there is another way to boost performance and lower energy consumption. The …

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  • 3D Memory Sparks New Thinking in HPC System Design

    February 21, 2017

    Whether being built for capacity or capability, the conventional wisdom about memory provisioning on the world’s fastest systems is changing quickly. The rise of 3D memory has thrown a curveball into the field as HPC centers consider the specific tradeoffs between traditional, stacked, and hybrid combinations of both on next-generation supercomputers. In short, allocating memory on these machines is always tricky—with a new entrant like stacked memory into the design process, it is useful to gauge where 3D devices might fit.

    While stacked memory is getting a great deal of airplay, for some HPC application areas, it might fall just …

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  • Memory is the Next Platform

    October 10, 2016

    A new crop of applications is driving the market along some unexpected routes, in some cases bypassing the processor as the landmark for performance and efficiency. While there is no end in sight for the CPUs dominant role, at least not until Moore’s Law has been buried along the roadside, there is another path—this time, down memory lane.

    Just as machine learning oriented applications represent the next development platform, memory appears to be the next platform for compute, especially with all the options coming down the pike. Phase change memory, memristors, resistive RAM, 3D XPoint, and others are on …

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  • Baking Specialization into Hardware Cools CPU Concerns

    September 21, 2016

    As Moore’s Law spirals downward, ultra-high bandwidth memory matched with custom accelerators for specialized workloads might be the only saving grace for the pace of innovation we are accustomed to.

    With advancements on both the memory and ASIC sides driven by machine learning and other workloads pushing greater innovation, this could be great news for big datacenters with inefficient legions of machines dedicated to ordinary processing tasks—jobs that could far more efficient with more tailored approaches.

    We have described this trend in the context of architectures built on stacked memory with FPGAs and other custom accelerators inside recently, and we …

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  • Deep Learning Architectures Hinge on Hybrid Memory Cube

    September 12, 2016

    We have heard about a great number of new architectures and approaches to scalable and efficient deep learning processing that sit outside of the standard CPU, GPU, and FPGA box and while each is different, many are leveraging a common element at all-important memory layer.

    The Hybrid Memory Cube (HMC), which we expect to see much more of over the coming year and beyond, is at the heart of several custom architectures to suit the deep learning market. Nervana Systems, which was recently acquired by Intel (HMC maker, Micron’s close partner), Wave Computing, and other research efforts all see a …

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  • Multicore Pioneer Tracks Architectural Path to Exascale

    February 23, 2016

    With over thirty years and more than thirty patents under his belt, Dr. Peter Kogge is one of the foremost leaders in high performance computing, both in terms of developing new ideas–and creating a vision for the most efficient routes to future extreme scale computing.

    In addition to designing the Space Shuttle I/O processor, the first multicore processor (EXECUBE), and more awards than can be gracefully mentioned here, Kogge has blazed trails through computing—both as an IBM Fellow and more recently as one of the lead thinkers behind how the future of exascale architectures will align with Department of Energy …

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  • Future Systems: What Will Tomorrow’s Server Look Like?

    February 4, 2016

    We can talk about storage and networking as much as we want, and about how the gravity of data bends infrastructure to its needs, but the server – or a collection of them loosely or tightly coupled – is still the real center of the datacenter.

    Data is useless unless you process it, after all. As more than a few companies that have built data lakes as a knee jerk reaction have come to realize.

    The server is where organizations spend the bulk of their budgets when they build platforms – excepting, of course, the vast sums they lavish on …

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  • There Is No Such Thing As Memory Performance

    October 5, 2015

    Petar Radokjovic, who leads the memory systems division at the Barcelona Supercomputer Center, described his desk, messy with the latest research on next-generation memory systems for high performance computing, and says that for a time, the sight of them was enough to give him an ulcer.

    Specifically, it has been the relatively recent string of published research (not to mention a wave of vendor material) espousing the tremendous “memory performance gains” that will come from the emerging series of stacked memory technologies, including the Hybrid Memory Cube and High Bandwidth Memory. It’s not that these are not potentially game-changing technologies, …

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  • A Wake Up Call for Hybrid Memory Cube Efficiency

    September 2, 2015

    There has been quite a bit of talk over the last couple of years about what role high bandwidth memory technologies like the Intel and Micron-backed Hybrid Memory Cube (HMC) might play in the future of both high performance computing nodes as well as in other devices, but the momentum is still somewhat slow, at least in terms of actual systems that are implementing HMC or its rival high bandwidth memory counterpart, High Bandwidth Memory (backed by a different consortium of vendors, including Nvidia and AMD).

    This is not a permanent situation, of course. Several vendors have pointed to stacked …

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  • Future Systems: Intel Ponders Breaking Up The CPU

    August 3, 2015

    When it comes to systems, the first thing that most people think of is compute. But if HPC is teaching us anything about system design – and one that is increasingly relevant as more and more data is being processed in memory in the corporate datacenter – it is that we don’t have a compute problem so much as a memory and I/O bandwidth problem.

    The memory bandwidth issue is particularly acute, and as we try to scale systems up into the exascale range and beyond, it will get much worse unless something changes. This was certainly the theme of …

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