Sponsored Post: We all know that inferencing and training AI models needs a lot of CPU muscle, but we don’t necessarily appreciate how important other components are in supporting AI and ML applications. …
Conventional wisdom says that trying to attach system memory to the PCI-Express bus is a bad idea if you care at all about latency. …
The jittery economy hasn’t been kind to most semiconductor companies, even those like AMD and Nvidia that are growing in the datacenter. …
The industry is impatient for disaggregated and shared memory for a lot of reasons, and many system architects don’t want to wait until PCI-Express 6.0 or 7.0 transports are in the field and the CXL 3.0 and beyond protocols that ride on it to reach out to external memory have been tweaked to do proper sharing across servers. …
If you are impatient for not just memory pooling powered by the CXL protocol, but the much more difficult task of memory sharing by servers attached to giant blocks of external memory, you are not alone. …
People have been talking about CXL memory expansion for so long that it seems that it should be here already, but with the dearth of CPUs that can support PCI-Express 5.0 peripherals we have to be patient a little bit longer. …
The Hot Chips 34 conference that is normally held at Stanford University is in full swing this week, and thanks to the coronavirus pandemic is being held entirely online. …
System architects are often impatient about the future, especially when they can see something good coming down the pike. …
The hyperscalers and cloud builders are not the only ones having fun with the CXL protocol and its ability to create tiered, disaggregated, and composable main memory for systems. …
Dynamic allocation of resources inside of a system, within a cluster, and across clusters is a bin-packing nightmare for hyperscalers and cloud builders. …
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