Optimizing DDR4 with server DIMM chipsets

DDR4 memory delivers up to 1.5x performance improvement over DDR3, while reducing power by 25% on the memory interface. The current generation of DDR4 memory deployed in datacenters runs at 2.4Gbps, although 3.2 Gbps silicon is expected to start shipping later this year (2016).

As Bob O’Donnel of TECHnalysis Research notes, the considerable increase in performance presents real challenges for the industry. More specifically, the shift to higher speeds degrades electrical signal integrity, especially with multiple modules added to a system. In practical terms, this means it’s becoming harder to achieve higher capacities at more advanced speeds. In order to overcome this limitation, says O’Donnel, memory designers use specialized clocks and dedicated memory buffer chips integrated onto the DIMMs.

“These server memory buffer chipsets play a critical role in high-speed DDR4 designs,” he explained. “They allow server designers to maintain the high-speeds that DDR4 offers, while also enabling the higher capacity designs that today’s [Big Data] applications require.”

According to O’Donnel, there are currently two categories of modern server DDR4 DIMMs. In a Registered DIMM (RDIMM), a Register Clock Driver (RCD) chip delivers a single load for the clock and command/address signals for the entire DIMM onto the data bus that connects between memory and the CPU. This technique facilitates a reduced impact on signal integrity versus an unbuffered DIMM, where all of the individual DRAM chips place multiple loads on clock and command signals.

On a Load Reduced DIMM (LRDIMM), each individual DRAM chip is equipped with an associated Data Buffer (DB) chip—in addition to the RCD on the module—to reduce the effective load on the data bus, enabling the use of higher capacity DRAMs. The combination of the RCD and individual DBs constitute a complete server DIMM chipset.

“With the server DIMM chipset enabled, data is not actually sent straight to the CPU from memory, just as gasoline isn’t sent straight to a car’s engine from its fuel tank,” said O’Donnel. “A properly designed fuel injection system sends gas to the engine in exactly the right form, quantity and speed that it requires and, in an analogous way, memory buffers serve to regulate the delivery of raw data from memory into and out of the CPU.”

As expected, the location of data buffers on DDR4 LRDIMMs also play a vital role in helping to achieve faster performance over DDR3 LRDIMMs.

“The [major] benefit is the reduced trace distance from each DRAM module to the memory bus and memory controller,” he explained. “While DDR3 LRDIMMs have a single centralized memory buffer that forces data to cross the distance of the DIMM module and back, DDR4 LRDIMMs have dedicated memory buffer chips located a very short trace line away from the data bus.”

Real world benefits include time savings that can be measured in nanoseconds, as well as optimized signal integrity facilitated by shorter trace lines. Both translate into improved real-world performance for time-sensitive applications. Performance is particularly important for today’s Cloud-based services, advanced analytics tools and other Big Data applications. Indeed, all are driving a higher set of expectations for servers.

“Throw in the looming prospect and opportunity of the Internet of Things (IoT) and the stage is set for a very challenging environment in today’s and tomorrow’s data centers and enterprise servers,” O’Donnel added. “Many of these new applications leverage very large in-memory databases to meet the performance expectations of today’s increasingly connected, mobile world.”

To be sure, microseconds count when providing real-time analytics on millions of financial transactions or offering real-time language translation via Cloud-based services. This is precisely why Rambus’ DDR4 chipsets for RDIMM and LRDIMM server modules are designed to deliver top-of-the- line performance and capacity needed to meet the growing demands placed on enterprise and data center systems. More specifically, our JEDEC-compliant DDR4 chipsets feature industry-leading I/O performance and margin, while utilizing advanced power management techniques. Additional key DDR4 server DIMM chipset features include support for DDR4 up to 2666 Mbps, multi-setting frequency-based power optimization, an operating temperature range of -5° C – 125°, full ROHS compliance and improved ESD/EOS beyond JEDEC requirements.

Interested in learning more about Rambus’ server DIMM chipsets? You can check out our official product page here.