• The Trials And Tribulations Of IBM Systems

    July 19, 2017

    IBM is a bit of an enigma these days. It has the art – some would say black magic – of financial engineering down pat, and its system engineering is still quite good. Big Blue talks about all of the right things for modern computing platforms, although it speaks a slightly different dialect because the company still thinks that it is the one setting the pace, and therefore coining the terms, rather than chasing markets that others are blazing. And it just can’t seem to grow revenues, even after tens of billions of dollars in acquisitions and internal investments over …

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  • The New Server Economies Of Scale For AMD

    July 13, 2017 Paul Teich

    In the first story of this series, we discussed the Infinity fabric that is at the heart of the new “Naples” Epyc processor from AMD, and how this modified and extended HyperTransport interconnect glues together the cores, dies, and sockets based on Eypc processors into a unified system.

    In this follow-on story, we will expand out from the Epyc processor design to the basic feeds and speeds of the system components based on this chip and then take a look at some of the systems that AMD and its partners were showing off at the Epyc launch a few …

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  • The Convergence Or Divergence Of HPC And AI Iron

    July 13, 2017

    Based on datacenter practices of the past two decades, it is a matter of faith that it is always better to run a large number of applications on a given set of generic infrastructure than it is to have highly tuned machines running specific workloads. Siloed applications on separate machines are a thing of the past. However, depending on how Moore’s Law progresses (or doesn’t) and how the software stacks shake out for various workloads, organizations might be running applications on systems with very different architectures, either in a siloed, standalone fashion or across a complex workflow that links the …

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  • The Heart Of AMD’s Epyc Comeback Is Infinity Fabric

    July 12, 2017 Paul Teich

    At AMD’s Epyc launch few weeks ago, Lisa Su, Mark Papermaster, and the rest of the AMD Epyc team hammered home that AMD designed its new Zen processor core for servers first. This server-first approach has implications for performance, performance per watt, and cost perspectives in both datacenter and consumer markets.

    AMD designed Epyc as a modular architecture around its “Zeppelin” processor die with its eight “Zen” architecture cores. To allow multi-die scalability, AMD first reworked its HyperTransport socket-to-socket system I/O architecture for use on a chip, across a multi-chip module (MCM), and for inter-socket connectivity. AMD has named this …

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  • Securing The HPC Infrastructure

    July 12, 2017 Dan Robinson

    In the world of high performance computing (HPC), the most popular buzzwords include speed, performance, durability, and scalability. Security is one aspect of HPC that is not often discussed, or else seems to be relatively low on the list of priorities when organizations begin building out their infrastructures to support a demanding new applications, whether for oil and gas exploration, machine learning, simulations, or visualization of complex datasets.

    While IT security is paramount for businesses in the digital age, HPC systems typically do not encounter the same risks as public-facing infrastructures – in the same way as a web server …

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  • High Expectations for Low Precision at CERN

    July 12, 2017 Jeffrey Burt

    The last couple of years has seen a steady drumbeat for the use of low precision in growing numbers of workloads driven in large part by the rise of machine learning and deep learning applications and the ongoing desire to cut back on the amount of power consumed.

    The interest in low precision is rippling through the high-performance computing (HPC) field, spanning companies that are running applications sets to the tech vendors that are creating the systems and components on which the work is done.

    The Next Platform has kept a steady eye on the developments the deep-learning and machine-learning …

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  • The X86 Battle Lines Drawn With Intel’s Skylake Launch

    July 11, 2017

    At long last, Intel’s “Skylake” converged Xeon server processors are entering the field, and the competition with AMD’s “Naples” Epyc X86 alternatives can begin and the ARM server chips from Applied Micro, Cavium, and Qualcomm and the Power9 chip from IBM know exactly what they are aiming at.

    It is a good time to be negotiating with a chip maker for compute power.

    The Skylake chips, which are formally known as the Xeon Scalable Processor family, are the result of the convergence of the workhorse Xeon E5 family of chips for two-socket and four-socket servers with the higher-end Xeon E7 …

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  • Momentum is Building for ARM in HPC

    June 30, 2017 Jonathan Beard, Roxana Rusitoru

    2011 marked ARM’s first step into the world of HPC with the European Mont-Blanc project. The premise was simple: leverage the energy efficiency of ARM-based mobile designs for high performance computing applications.

    Unfortunately, making the leap from the mobile market to HPC was not an easy feat. Long time players in this space, such as Intel and IBM, hold home field advantage: that of legacy software. HPC-optimized libraries, compilers and applications were already present for these platforms. This was not, however, the case for ARM. Early adopters had to start, largely from scratch, porting and building an ecosystem with a …

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  • Giving Out Grades For Exascale Efforts

    June 27, 2017

    Just by being the chief architect of the IBM’s BlueGene massively parallel supercomputer, which was built as part of a protein folding simulation grand challenge effort undertaken by IBM in the late 1990s, Al Gara would be someone whom the HPC community would listen to whenever he spoke. But Gara is now an Intel Fellow and also chief exascale architect at Intel, which has emerged as the second dominant supplier of supercomputer architectures alongside Big Blue’s OpenPower partnership with founding members Nvidia, Mellanox Technologies, and Google.

    It may seem ironic that Gara did not stay around IBM to help this …

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  • U.S. Military Sees Future in Neuromorphic Computing

    June 26, 2017

    The novel architectures story is still shaping out for 2017 when it comes machine learning, hyperscale, supercomputing and other areas.

    From custom ASICs at Google, new uses for quantum machines, FPGAs finding new routes into wider application sets, advanced GPUs primed for deep learning, hybrid combinations of all of the above, it is clear there is serious exploration of non-CMOS devices. When the Department of Energy in the U.S. announced its mission to explore novel architectures, one of the clear candidates for investment appeared to be neuromorphic chips—efficient pattern matching devices that are in development at Stanford (NeuroGrid), The …

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