It was just over a year ago that the RISC-V Foundation, the group shepherding the chip architecture in what over the past decade has become an active and crowded processor market, ratified the base instruction set architecture (ISA) and related specifications. It was a significant step for a relatively new architecture that is provided under open-source license that don’t require companies to pay fees if they want to build products based on the ISA or modify ISA itself and that intended to stretch from microcontrollers to datacenter systems.
The proponents behind RISC-V are positioning the architecture as an alternative to both X86 used by Intel and AMD that is not open and Arm, which provides its chip designs to manufacturing partners but with a licensing fee that can reach into the millions of dollars. A growing number of companies – such as Nvidia (which reportedly is considering making a bid for Arm) and Western Digital – are beginning to embrace the architecture. Another company that is making a move with RISC-V is giant Chinese hyperscaler Alibaba. Tensions between the United States and China over technology are growing and Chinese officials are continuing to push for more of the products being used in the country be homegrown and companies like Alibaba and SiFive are embracing the RISC-V architecture.
Alibaba in July introduced its first RISC-V-based product, the XT910 (the XT stands for Xuantie, which is a heavy sword made using dark iron), a 16-core design that runs between 2.0 GHz and 2.5 GHz etched in 12 nanometer processes and that includes 16-bit instructions. Alibaba claims the XT910 is the most powerful RISC-V processor to date. The company spoke more about the processor at this week’s virtual Hot Chips 2020 conference, giving an overview of the processor, an idea of how it stacks up to Arm’s Cortex-A73 (which is designed for high-performance mobile devices), and a glimpse of what the company is planning for down the road. It also gives us a reference point from which to think about RISC-V server processors.
The chip was designed by T-Head, a young semiconductor unit running under Alibaba’s DAMO Academy. Yu Pu, edge product lead for T-Head, spoke about the chip at the Hot Chips 2020 event, saying Alibaba is looking to RISC-V as the basis for its cloud and edge computing infrastructure. Pu admitted that it was early in the development of the architecture, but that company engineers were confident in the technology and how they can work with the open-source community to improve it.
“Although the RISC-V is not yet mature enough in terms of technology and ecosystem, we believe it has great potential,” he said. “The intention of this work is to contribute to the high-end and high-performance embedded computing cores based on RISC-V through open-source collaboration.”
Like a lot of infrastructure component vendors, Alibaba is looking at the rapid changes in the industry brought about by the rise of the cloud, mobility and the Internet of Things in terms of the massive amounts of data that is being generated – with projections of hitting 175 zettabytes by 2025 – and the compute, networking and storage capabilities that will be needed to run the technologies like artificial intelligence (AI), machine learning, automation and analytics to collect, store, manage and analyze all that data. It’s the increasingly intelligent IoT and the “astronomic computing traffic” that are driving the research for more low-power and low-cost infrastructure, he said.
“RISC-V is very attractive at this point in time because as an alternative to closed and costly ISAs, the open and free ISA RISC-V accelerates processor innovation through open-standard collaboration,” Pu said. “The scalability, extensibility and modularity enable processor customers … optimization for domain-specific workloads, such as machinery accelerators, network processing, security outlay, storage controllers and so on, thereby largely posting processing efficiency and reducing design costs. RISC-V is also very easy to accompany with other domain-specific IPs from partners, both from technical angles and business perspective. RISC-V is nowadays becoming a bit like … Unix and Unix operating system. It is also fully supported by our AliOS [Alibaba’s Linux distribution]. As the toolchain is getting more and more mature, it further improves the software experience and drives down software development costs.”
The XT910 supports RISC-V 0.7.1 Vector Extension, includes a vector engine for AI acceleration and is based on 12 nanometer FinFET processes from Taiwan Semiconductor Manufacturing Corp. It’s a cluster-based multi-core design with up to four cores per cluster and each core supports 32 KB to 64 KB of L1 data cache and 32 KB to 64 KB L1 instruction cache. It includes a hybrid branch predictor, implementing more than one predictor mechanism to improve performance and efficiency. The chip also offers the RISC-V Turbo feature that uses such tweaks as syncing multiple cores and faster memory access to ramp up performance, but it also can be turned off to enable the chip to be completely compatible with other RISC-V chips.
It features a deep superscalar out-of-order pipeline with eight fetch, three decode, and eight issue instructions per cycle on the front end and out-of-order memory access, dedicated branch processing and out-of-order vector computing on the back end. The multi-core interconnect features decoupled processor interface units (PIUs), the MOESI Coherence Protocol and a configurable L2 cache of up to 8 MB.
AI is key to adding the intelligence needed to enable systems to manage and analyze the massive amounts of data being generated. Below are the details of the AI-optimized Vector Extension, which includes more than 300GFLops of FP16 compute power per cluster.
Pu said the chip is the highest performing RISC-V processor on the market now, though he added that SiFive is developing its U84 processor that might deliver higher performance. However, there are no details on the U84 so it couldn’t be included in the graph below.
Alibaba compared the chip’s capabilities with that of the Arm Cortex-A73, which is the foundation of Huawei’s Kirin 970 AI-enable mobile platform that was introduced in 2017. The XT910 chips used in the tests were configured to the same L1 cache sizes. The results below show the Alibaba chip outdistancing the Cortex-A73 in a number of the benchmark parameters, though Pu admitted that the XT910 is still a young chip and needs more work. But the initial numbers are encouraging, he said.
How the XT910 will roll out still remains to be seen. The company is using the chip in the Alibaba Cloud and it can be used with the company’s Wujian SoC platform. In addition, the company plans to make the chip’s architecture available to the open-source community and is working with community groups toward this goal, Pu said.
“The intention of Xuantie series is not to compete with any non-RISC … project but rather contribute to the open source RISC-V community,” he said.
The XT910 chip also is the first in a family that the company plans to roll out. Pu talked about the XT902, a low-power chip on the other end of the spectrum from the XT910 that comes with a Trusted Execution Environment and is in the same microcontroller class as Arm’s Cortex-M0. The company also has three others in the works – including the XT903, 905, 907 and 908 – that will come with different embedded performance and power levels.
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And not a word about MIPS???
The Chinese are interested in RISC-V because it is not subject to the whims of the US administration. MIPS is.
I read earlier this year that a Chinese company was able to gain control of all MIPS IP after buying it from the company that controlled it…
Don’t China’s homegrown supercomputer chips use MIPS?