Ayar Labs, a silicon photonics startup based in Emeryville, California, is getting set to tape out its electro-optical I/O chip, which will become the basis of its first commercial product. Known as TeraPHY, it’s designed to enable chip-to-chip communication at lightning speed. The company is promising bandwidth in excess of one terabit per second, while drawing just a tenth the power of conventional electrically-driven copper pins.
The problems of copper pins and electrical signaling encompasses power, data reach, and chip real estate limitations. As the performance of processors advance, faster data rates are required; more data is needed to feed the chips and more data is generated during processing. Although growth in processor performance has slowed over the past several years due to the erosion of Moore’s Law, electrically-driven chip communication has still been unable to keep pace. According to Ayar Labs chief strategy officer and company co-founder Alex Wright-Gladstein, there is a consensus that the highest data rate that will be able to exit a chip package is 100 Gb/sec. “The industry really didn’t even agree that we would reach a limit before 2018, but that debate has gone away entirely,” she told The Next Platform.
Looking just slightly into the future, a 10 teraflops processor that could be the basis for an exascale supercomputer would need something on the order of 10 Tb/sec of chip I/O to be usable. But that would require around 2,000 copper pins, which together would draw about 100 watts – not the chip just the I/O pins. If that sounds problematic, that’s because it is.
Silicon photonics, the melding of optical communications and semiconductors for chip-level I/O, is widely viewed as the solution. Intel, IBM, Hewlett Packard Enterprise, Fujitsu, and others have been working on the technology for years, but cost-effective solutions have been elusive, mainly because these devices tend to be constructed with exotic compounds and rely on special semiconductor manufacturing techniques. That’s fine for long-haul optical fiber communications, but for short-haul electro-optics, costs need to align with server and chip pricing.
Here is where Ayar stands out from its competition. The startup has managed to build its devices using standard CMOS – the same manufacturing technology used to etch integrated circuits on commercial microprocessors. And it doesn’t need to be a leading-edge process node either. The first TeraPHY chip will use GlobalFoundaries’s 45 nanometer CMOS SOI process, the same one used by the Blue Gene/Q processor back when IBM had this manufacturing technology in-house. As a consequence, the company has apparently avoided the major cost roadblock that vexes other electro-optical solutions.
Ayar’s technology has its roots in a 10 year, $20 million project funded by DARPA that brought in researchers from MIT, UC Berkeley and the University of Colorado, Boulder. The project, known as Photonically Optimized Embedded Microprocessors (POEM), aimed to solve the I/O bottleneck at the level of the processor. The research team demonstrated a prototype electro-optical chip, which was subsequently described in an academic paper published in December 2015. Wright-Gladstein, an MIT MBA grad, convinced researchers Mark Wade, Chen Sun, Rajeev Ran, Vladimir Stojanovic, and Milos Popovic that the technology should be commercialized and together they cofounded Ayar Labs.
According to the company’s website, the initial TeraPHY device will be available as a 1.6 Tb/sec optical transceiver, comprised of four 400 Gb/sec transceivers per module. All the componentry except for the light source (which is supplied by a separate 256-channel laser module, called SuperNova) has been integrated into the device. That includes the electrical interfaces, the optical modulators, the photodetectors, and the dense wavelength division multiplexing (DWDM) wavelength multiplexer/demultiplexer, as well as all the driver and control circuitry.
Wright-Gladstein says the solution not only delivered a high performance electro-optical device, but was able to do so in an area 1/100 the size of a typical long-haul optical transceiver. “Because of that 100X size difference, you’re now crossing that threshold set by electrical SerDes, and you’re making an optical I/O that’s smaller than your electrical I/O,” she says.
Forgoing the more exotic designs of other silicon photonics solutions required some extra tinkering. The design uses optical “micro-ring resonators” implemented in CMOS to achieve the extreme density of the TeraPHY. These resonators can be “finicky” due to thermal issues and size, but according to Wright-Gladstein, they’ve implemented a patented thermal tuning technology that stabilizes the resonators and makes them very reliable.
Physically, TeraPHY is in the form of an “chiplet,” a chunk of silicon that is meant to be integrated into the kind of multi-chip modules that are becoming more commonplace in high-end processor packages. The TeraPHY tape out is slated for the end of the current quarter (Q1 2019), with the first integrated products from Ayar’s silicon technology partners due to hit the street in 2020.
The identity of those partners is still a mystery, although in recent conversation we had with Wright-Gladstein and Ayar CEO Charlie Wuischpard, they indicated that their first commercial offering will initially show up in datacenter switches. That would make a lot of sense, inasmuch as TeraPHY is essentially an optical transceiver, something switch vendors would already be familiar with integrating into their boxes.
More generally though, TeraPHY is meant to be integrated into all kinds of multi-chip packages — CPUs, GPUs, FGPAs, and custom ASICs, as well as DIMMs – destined for datacenter duty. Not only will the optical communication greatly speed up chip-to-chip and chip-to-memory data transfers, it will also allow for the disaggregation of server processors, memory, and local storage, paving the way for more efficient and flexible designs. ‘What we [intend to] do is enable the Intels of the world, the AMDs, the Nvidias, the HPEs, and the Crays to build new architectures based on this technology,” explained Wuischpard.
Ayar’s main customer base, at least initially, will be the owners of high performance computers and hyperscale cloud datacenters. These are the customers with the most insatiable needs for bandwidth, an obsessive concern for keeping power use in check, and a healthy appreciation for optical communication technology. That makes them a good match for these first-generation silicon photonics products. Ayar pegs the total addressable market at $29 billion.
Further down the road, the company is eyeing other application areas, including autonomous vehicles, IoT, and various kinds of mobile devices. “We want to get every chip communicating using light,” says Wright-Gladstein.
Ideally, Ayar would be able to sell its wares to multiple chip and system vendors, but if the technology is even half as capable as Ayar portrays it, the company will be acquired before too much longer. Although practically any server, network, storage, or telecom vendor could benefit from owning their own silicon photonics IP, the most value would be derived from chipmakers like Intel and AMD. If the TeraPHY chiplets deliver as advertised, they could substantially improve the capabilities of their respective datacenter offerings: Xeon processors and Stratix and Arria FPGAs in Intel’s case, and EPYC processors and Radeon GPUs in AMD’s case. Heterogeneous packages (CPU-FPGA and CPU-GPU) would also be good targets.
Given AMD’s enthusiasm for the chiplet package concept in its EPYC line, and its need to come up with stronger differentiation for its datacenter silicon relative to its more dominant rivals (Intel and Nvidia), it might be the ideal buyer of an optical I/O chiplet company. Intel, meanwhile, has its own silicon photonics program in motion, so might be reticent to add a competing technology.
With the TeraPHY chiplets sampling later this year and 2020 commercial deployments just around the corner, the next couple of years will likely demonstrate whether Ayar has something worth acquiring – either the whole company or its products. And if it does, the buyers will line up accordingly.
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“Looking just slightly into the future, a 10-teraflop processor that could be the basis for an exascale supercomputer would need something on the order of 10 Tbps of chip I/O to be usable.”
Into the future? We’re already integrating GPU:s with ~14 TFLOPS (FP32) of compute performance into todays ~200 PFLOPS (0.2 ExaFLOPS) system like summit and sierra.
Interesting. Claims about Cooper’s demise are a bit premature.