Disruptive Technologies on the Post Exascale Horizon

Although the timeline for reaching exascale class computing continues to stretch farther into the future, research teams are keeping an eye on what technologies will shape the machines of the post-exascale timeframe, which is in the 2022-2030 timeframe.

While many of the technologies stated in a comprehensive report about post-exascale supercomputers are already in process, albeit in various stages of development and adoption, there is little consensus about which mode of computing will lead us into an era of unprecedented data and simulation potential. Still, the effort on behalf of the EuroLab-4-HPC program is notable in its divisions between where the promise lies for disruptive, sustaining, and completely new supercomputer technologies. As it turns out, there is equal potential placed on all three; from the entirely different (quantum, neuromorphic and resistive computing) to the same old (CMOS scaling) to the disruptive (non-volatile memory, die stacking, and photonics).

The exascale-focused Horizons 2020 program funded the two-year EuroLab-4-HPC undertaking to keep tabs on the research agenda for future systems across European high performance computing (HPC) centers. As part of their ongoing work, they have released detailed analysis of where they expect a host of technologies to fit into the post-exascale landscape. While the full report offers extensive commentary on all of these, we wanted to share some of the key areas they are watching here.

hpcfeThe team has created a subset group of “sustaining technologies” which are those that follow an innovation curve that is generally expected. These include CMOS scaling trends and die stacking and 3D chip technologies. Disruptive technologies, on the other hand can create new lines of HPC hardware, the team says, pulling non-volatile memory and photonics in as representative technologies—both of which are actively in development and expected in pre-exascale systems. There are also disruptive technologies that can completely upend standard CMOS for processor logic, including the use of nanotubes, graphene, and diamond transistor approaches.

As we move down to the 10nm FinFET chips and smaller, the manufacturing challenges of existing CMOS scaling will mount, which means this will be an area of great emphasis for future exascale systems. The team notes that current roadmaps don’t take computing smaller than 6nm, so new density alternatives are needed. They say one trend is to look to 3D integration where “a revolutionary DRAM/SRAM replacement will be needed. As a result, non-silicon extensions of CMOS, using other materials including carbon nanotubes and non-CMOS platform, including molecular electronics, spin-based computing, and single-electron devices” will all be considered. It is this key issue that drives many other far-future approaches, including quantum, neuromorphic, and resistive computing.

The team gives significant weight to die stacking, focusing both on near-term and long-term technologies. In addition to compute, they note that 3D stacking will also apply to flash memory given the limitations at 16nm for existing 2D NAND flash. “3D stacking ha a series of beneficial impacts on the hardware in general and on the possibilities of designing future processor-memory architectures in particular…3D stacking also enables heterogeneity by integrating layers, manufactured in different processes, which would be incompatible among each other in monolithic circuits.”

With that in mind, they also remark on the potential of non-volatile memory (NVM) technologies, which faces the hurdle of endurance and performance decreases in shrinkage. Here, memristors and phase change memory are key technologies. “Among the most prominent memristor candidates and close to commercialization are phase change memory, metal oxide resistive random access memory, and conductive bridge random access memory, but all of these have years before wider market adoption. The team also provides detail on other approaches, including spintronics and “nano ram”, which is a proprietary technology from Nantero that uses a carbon nanotube fabric.

Ultimately, they note that it is foreseeable that “other NVM technologies will supersede current flash memory. Phase change memory might be 1000X faster and 1000X more resilient. Some NVM technologies have been considered as a feasible replacement for SRAM.” This section is perhaps the richest in terms of technology overview, options, and market potential than any other in the report. On a related note, photonics are explored in some depth as potential market-changers for large-scale computing in the post-exascale era. This is something that already has a great deal of development happening well.

The report outlines in solid detail alternatives to current modes of computing, including quantum, neuromorphic, and resistive computing. It would be redundant to encapsulate all of their points here, but for those interested in what is on the horizon for high performance and large-scale computing in the next decade, this is required reading and begged for a pointer. Also of interest from the same EuroLab4HPC group is another comprehensive roadmap report that includes many of the disruptive technologies described here in the context of broader architectural trends.

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