The Hardware Geek’s Guide to SC15

It has been a noteworthy year in hardware in the world of high performance computing, although to be fair, much of the attention has been centered on emerging architecture and future systems that are set to start appearing as early as this time next year.

In culling through the dense menu of delicious session offerings at the annual supercomputing conference (SC15) in Austin, we pulled some of the meatiest picks to help shape a sense of what HPC is watching now—and as we move into the new era of pre-exascale supercomputers.

With that in mind, all that time spent in solitary scrolling seemed a waste not to share, so here are some choice sessions—and where you’re quite likely to find at least one of us lurking about, sleep-deprived but caffeinated beyond reasonable limits. Come hang with us on Wednesday night for our casual Happy Hour with The Next Platform at Javlina (within walking distance from the center) and we’ll compare notes on how the suggestions below turned out.

So, where to start?

First, the Emerging Technologies track at SC15 is always laden with hardware goodies and this year the committee took a new step forward in that direction by adding a “SoC for HPC” theme. If this is of interest, there is an extensive lineup throughout the week, all in the same location from 9:00 a.m. until 5:30 p.m. so you can, if you’re fortune enough to not be running your ass ragged during a show like this (ahem), park yourself and get up to date on dozens emerging architectures that pull from embedded and other worlds and find a fit for HPC applications.

Among the novel architectures being explored this year at SC15 of particular note is GoblinCore-64. As the session chairs describe, current processor approaches that are reliant on multi-level data caches and relatively low levels of concurrency have inherent limitations in that they are only generally well-suited to cache friendly applications while those with irregular memory access patterns can suffer, especially as data volumes grow and can’t fit in cache. The GoblinCore-64 folks have figured out some clever workarounds for this (to get a flavor, take a look at this other emerging technology from earlier this year—not from SC but of related note). For a precursor deep dive, the authors have published their technical specifications here.

Another notable newcomer to the HPC processor game with an SoC slant is the Exanode SoC. Funded under Europe’s Horizon 2020 program, the goal is to create an ultra-low power, high performance processor. As the research team behind it describes, the approach combines a “coordinated application of several innovative solutions already in HPC; ARM-v8 low power-processors for energy efficiency; 3D interposer integration for compute density; and an advanced memory scheme for Exabyte-level capacities.” The implementation is comprised of stacked “chiplets” to create a 3D integrated circuit. The team will show this off, as well as detail the software stack for multi-node use as well as highlight performance on “HPC mini-apps” on the platform.

If you have been going to HPC events over the years, at some point you’ve probably encountered Ronald P. Luijten, who has been working on low-power server chips for several years from within IBM Research labs. This year he will be describing the prototype DOME hot water-cooled multi-node 64-bit microserver, based on a Freescale SoC part. The nodes have just come out of hardware validation and he will be sharing updates about this as well as offering a demo.

A slightly less esoteric—and definitely better funded effort—is the Automata processor from Micron, which will be detailed in the SoC and Emerging Technologies track at SC15. Seven years after formulating a plan and application set, as well as programming model for the non-deterministric finite automata processor, they are finally in fabrication and situated in a few key research centers. Although these have been explored in sessions before, and received a fair bit of attention, we are hoping to discover more about the actual performance in some real-world context during the session.

Perhaps the best place to start with the birds of feather sessions is with one of the definite emerging areas, not just in HPC, but in the general datacenter space, at least according to Intel, whose CEO stated that by 2020 one-third of all cloud datacenters would be outfitted with field programmable gate arrays (FPGAs). This is definitely something we’ll be watching next week and that will kick off with a general exploratory session called simply,  “Reconfigurable Supercomputing” which takes place on Tuesday. This is going to be worth delaying dinner to catch. In addition to exploring where one might expect, with FPGAs, this session will look across the broader landscape of reconfigurable devices from Altera and Xilinx as well as touch on the development of the Novo-G3 processor, which is housed at the NSF’s CHREC center.

And speaking of accelerators and co-processors, session leaders from TACC, NREL, and Berlin’s Zuse Institute will oversee a birds of feather set of topics on Wednesday featuring discussions about new and emerging uses for Intel’s Knights Landing processors with a look ahead and post-KL architectures before spinning out to the Xeon Phi Users Group.

For one hidden bit of HPC hardware goodness in commercial supercomputing context, there will be a gathering of oil and gas experts to talk about the high performance computing roadmap in that industry. While we expect a fair bit of the talk will be around applications, it might be useful to attend to better understand how that industry is thinking about next-generation architectures—and whether their time-honed applications will be primed to take advantage of higher core and memory capabilities and potential new acceleration options. A similar expert session will look at some of the same trend but as they relate to the biosciences and pharmaceutical fields and will project the role of HPC in the area by 2020. The attraction here is that the session chairs are from competing drug companies, Bristol-Myers Squibb, Pfizer, and Merck.

Even though it’s not until Wednesday, one of the defining sessions in terms of forthcoming architecture trends, will be moderated by folks from Berkeley and Sandia labs. “Supercomputing After the End of Moore’s Law” will feature a string of presentations that look at emerging technologies that move HPC beyond the Moore’s Law limits, including the introduction of low-power transitions, more effective use of 3D integration, and other technologies. As one might imagine, the software refactoring involved will be part of the discussion, but this is at the top of this year’s list of sessions for new ideas—or at least, lively conversation.

We probably shouldn’t overlook some of the non-chippery learning that will happen at SC15. Although it’s not necessarily the focus here, we will be found during a presentation of the InfiniBand roadmap and some notable overviews of emerging technologies, including this open source implementation of a hybrid memory cube controller.

It is not all about new chips and architectures, however. As we know, a growing concern for next-generation supercomputers is power and energy reduction and management. Accordingly, there are several sessions at SC15 that focus on power and cooling, some from vendors, others with a more theoretical bent. For instance, Cray, ORNL and Leibniz Supercomputing Center folks will be present on some of the finer points of liquid cooling using CDUs with constant temperatures and flow rates. This is not as straightforward as it sounds because it is difficult to determine the ROI of such investments, especially given different application and load demands. There are some other compelling energy efficient supercomputing and power and cooling topics to be found in the emerging technologies arena as well, including this upcoming presentation on mineral oil-based direct liquid cooling.

On that power, cooling, and efficiency note, to see how hot hardware performance stacks up against the Green 500 supercomputing benchmark, Wednesday afternoon the rankings for this metric will be announced. Last year the unique Shobu supercomputer at RIKEN with its blend of Haswell and PEZY-C processors topped the list—this is always an interesting ranking because it calls attention to notable systems that might have slipped through the Top 500 cracks attention-wise but have taken clever approaches to energy efficient performance.

One of the most obvious things that we did not mention here is the annual Top 500 announcement, which will provide details on the world’s fastest supercomputers ranked by the LINPACK benchmark. This happens on Tuesday evening, but we will have the list and details first thing Monday morning, so do stay tuned. On that note, a companion benchmark, HPCG, which is touted as being a more balanced (at least in the context of real-world applications) metric in that it goes beyond mere floating point capability to determine system performance, will also be presented the following afternoon. One can assume updates to the benchmark will be shared—and that plenty more systems will have submitted this time around.

It’s tempting to say, “that’s it” but there will be additions to this list as we go. Inevitably, every year I’ve put together a top sessions pick (including for HPCwire) a certain amount of hate mail streams in because I missed someone’s session. Maybe instead of sending me hate mail directly, add a comment pointing to whatever else you think is relevant to the hardware folks—not that I don’t love a good juicy nasty letter, but maybe others will find a session we’ve missed here of interest as well.

See ya’ll soon–